1. Field of the Invention
The present invention relates to large scale integrated (LSI) complementary metal-oxide semiconductor (CMOS) technology. More particularly, the present invention relates to apparatus and techniques for stabilizing the output characteristics of a plurality of CMOS LSI chips. The present invention has particular application, although is not limited to providing separate LSIs which are used to drive a common unterminated data bus, where the output characteristics of the CMOS LSIs are advantageously stabilized or matched in order to improve system performance.
2. State of the Art
It is well known that in the manufacture of a single LSI chip, it is possible to match and scale the characteristics of the transistors on that chip. The matching and scaling properties result from the fact that all devices on a single chip are subject to the same manufacturing process, as well as operating temperatures (T) and voltages (e.g., V.sub.DD). However, it is also well known that the absolute properties of transistors on a chip cannot be closely controlled, and that a matching of transistor characteristics (e.g., R.sub.ON) on different chips is not presently possible. Indeed, the characteristics on CMOS devices of different LSI chips can vary by as much as three to one.
FIG. 1 illustrates a situation where it would be beneficial to be able to stabilize (match) the output characteristics of different CMOS chips. FIG. 1 is a simplified prior art diagram of a plurality of CMOS devices 50a, 50b, 50c coupled to a common unterminated bus 54, where each CMOS device 50 has an open drain driver T.sub.3 for driving the common unterminated bus 54. For illustration purposes, the bus 54 is pulled up with a current I.sub.PU by a clamped current source 56 from a voltage V.sub.C through a diode having a voltage differential of V.sub.D. For this example, the bus 54 can be assumed to act as a lumped load capacitance C.sub.T. The CMOS device 50 drives the bus 54 by turning on the driver transistor T.sub.3 which is in turn controlled by a two transistor gate controller having transistors T.sub.1, T.sub.2. The transistors T.sub.1 and T.sub.2 are arranged to function as an inverter, and selectively couple the gate of the driver transistor T.sub.3 to V.sub.CC or ground. In particular, when a high data signal is applied to the gates of transistors T.sub.1, T.sub.2, the p-type transistor T.sub.1 turns OFF and the n-type transistor T.sub.2 turns ON. The voltage at the gate of transistor T.sub.3 is thereby pulled low by transistor T.sub.2 which turns transistor T.sub.3 OFF. When transistor T.sub.3 is OFF, the voltage level of the bus 54 remains HIGH. However, when a low data signal is applied to the gates of transistors T.sub.1, T.sub.2, the p-type transistor T.sub.1 turns ON and the n-type transistor T.sub.2 turns OFF. The voltage at the gate of transistor T.sub.3 is thereby pulled high by transistor T.sub.1 which causes transistor T.sub.3 to turn ON. When transistor T.sub.3 is ON, the voltage of the bus 54 is pulled LOW, as transistor T.sub.3 is coupled to ground.
The normal high level voltage of the bus is represented by V.sub.HO which equals V.sub.C plus V.sub.D, and the normal low level voltage of the bus is represented by V.sub.LO and can be graphically determined by the intersection of the pull-up current I.sub.PU and the R.sub.ON characteristic of the particular T.sub.3 device (as seen in FIG. 5 discussed below). Thus, V.sub.LO is poorly defined. The rising change in voltage of the bus when the bus is allowed to go HIGH and is pulled HIGH by the current I.sub.PU will generally be a linear ramp (dr/dr=I.sub.PU /C.sub.T), where I.sub.PU is the pull-up current of the bus. The rising time t.sub.R may be expressed as C.sub.T (V.sub.HO -V.sub.LO)/I.sub.PU. The falling change in voltage on the bus over time (i.e. when the bus is driven LOW by driver T.sub.3), however, is generally ill defined and non-linear due to the non-linear characteristics (e.g., R.sub.ON and I.sub.D,SAT) of the drivers T.sub.3. Moreover, the ON characteristics of different driver devices T.sub.3 are different because each device is subject to different V.sub.CC, temperature, and semiconductor chip processing parameters, and may vary by as much as 3:1.